资源描述
1 / 21 EDA EDA EDA CAX EDA 1 EDA 2 EDA 3 EDA 4 + EDA 1 2 3 -15% 0% 15% 31% 46% 62% 2019-10 2020-02 2020-06 2020-10 3002 / 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 / 21 . . . . . . . . . . . . . . . .1 / 21 1 EDA 1.1 EDA EDA 1 EDA EDA 2 EDA 200 2011 3 EDA 0 10 20 30 40 50 60 70 80 90 EDA EDA2 / 21 1.2 EDA EDA EDA 1 EDA CAD-CAE-ESDA- EDA 4 EDA EDA3 / 21 5 EDA 2 EDA 2.1 EDA 70 4000 EDA 6 2020 EDA 70 40004 / 21 7 2020 3600 8 2014 9 10 EDA EDA 2000 2500 3000 3500 4000 2014 2015 2016 2017 2018 2019 2020 3000 4000 5000 6000 7000 8000 9000 10000 2014 2015 2016 2017 2018 2019 2020 26% 28% 30% 32% 34% 36% 0 200 400 600 800 1000 1200 1400 2014 2015 2016 2017 2018 2019 2020 % 33% 36% 39% 42% 45% 0 500 1000 1500 2000 2500 3000 3500 4000 2014 2015 2016 2017 2018 2019 2020 5 / 21 11 2020 EDA 72 12 2020 EDA 66 、 EDA 13 EDA 14 EDA % 2.2 EDA 2.2.1 EDA 1 EDA 1.5% 1.6% 1.7% 1.8% 1.9% 2.0% 2.1% 60 62 64 66 68 70 72 74 2018 2019 2020 EDA EDA % 0.68% 0.70% 0.72% 0.74% 0.76% 40 45 50 55 60 65 70 2018 2019 2020 EDA EDA % 0 10 20 30 40 50 60 70 80 2018 2019 2020 0% 20% 40% 60% 80% 100% 2018 2019 20206 / 21 50% 15 16 50% 2 EDA 17 28nm7 / 21 18 2015 19 、 2.2.2 EDA EDA 1 EDA 20 EDA % 2 0 500 1000 1500 2000 2500 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 2018 2019 20208 / 21 21 EDA EDA 2 EDA 2.2.3 EDA9 / 21 3 2025 IP 8 40 22 2018 EDA EDA 23 6% 7% 8% 9% 10% 11% 12% 2 3 4 5 6 7 8 2018 2019 2020 EDA 10 / 21 4 EDA EDA ICCAD EDA 24 EDA 25 EDA 、 3 3.1 80% 18 21 24 27 30 2018 2019 2020 EDA 2100 2300 2400 700 1400 2000 0 500 1000 1500 2000 2500 3000 2018 2019 202011 / 21 26 CR3 80% CR5 85% 27 EDA 80% 202012 / 21 28 2018 % 3.2 29 EDA 2.90% 3.80% 5.59% 0.96% 1.00% 1.44% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 2018 2019 2020 Siemens EDA Cadence Synopsys13 / 21 30 % 31 % EDA EDA 5 EDA Fabless Synopsys CoCentric HDL HDL RTL Synopsys LEDA Synopsys VCS Cadence NC-Verilog Verilog XL Mentor Modelsim Logic Synthesis RTL Gate netlist Synopsys Design Complier Cadence PKS Encounter RTL Complier Synplicity Synopsys 2008 Synplify STA Static Timing Analysis setup time hold time Synopsys Prime Time Cadence Encounter Timing Formal Verification HDL HDL Synopsys Formality Cadence Encounter Conformal DFT Design For Test Synopsys DFT Compiler Floor Plan IP RAM I/O Synopsys Astro Cadence Encounter Silicon Ensemble CTS Clock Tree Synthesis Synopsys Physical Compiler Place & Route Synopsys Astro , Synopsys Star-RCXT 30% 35% 40% 45% 50% 55% 60% 2018 2019 2020 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 2019 202014 / 21 LVS Layout Vs Schematic DRC Design Rule Checking ERC Electrical Rule Checking Synopsys Hercules Cadence Assura Mentor Calibre 32 6 EDA 25.51 25.51 EDA15 / 21 33 EDA 7 3.316 / 21 8 2018 2019 2020 2018 2019 2020 0.8 1.3 2.3 0.1 0.3 0.6 417 / 2118 / 21
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